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Sample assignments in VHDL
Huzlík, Petr ; Macho, Tomáš (referee) ; Holek, Radovan (advisor)
This bachelor’s study connects on semestral project and is focused on VHDL language and FPGA and CPLD circuits by Xilinx. The aim of this study is to describe how to work with profossional design tool WebPack. Documents detaily describes how to create new project on advanced level - with emphasis on methodiology and examples from practice in VHDL lenguage.
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Transformation between the Microprocessor's Description Language and the Hardware Language
Novotný, Tomáš ; Masařík, Karel (referee) ; Hruška, Tomáš (advisor)
The Master's thesis Transformation of the microprocessor's description language to the hardware description language is aimed at design of application specific microprocessors with using ISAC language. It deals with design and implementation of transformation which converts description of microprocessor in ISAC language into equivalent description in VHDL language. The chapter Summary of research problems describes chosen problems, showing up some notions connected with problems and presents suggestion of transformation mentioned above. The chapter Suggestion of solution presents new extension of ISAC language. There is also described the way of design solution of transformation and solution of implementation of VHDL generator which performs transformation. Conclusion of thesis discusses next points of future work reached results.
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Additional LCD Display for Laboratory Kit with a Programmable Device
Pajskr, Jaroslav ; Kubíček, Michal (referee) ; Kolouch, Jaromír (advisor)
The main part of the digital application is its user interface. Users can check the status of the programme or change its state. There are many ways to obtain a suitable interface. During the design stage the simplest interface is chosen that provides the necessary functions. In most cases the interface contains a display. This diploma thesis deals with the design of an extension board to plug in a display to a programmable device, a control algorithm for the display and the design of a simple display interface. There are two ways to design software. The first of them is achieved by the processor PicoBlaze, which contains all the required functions. The second solution is by the state machine written in VHDL language. Both solutions can be used in the same way, but the latter solution is quicker and requires less hardware resources.
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Thermal sensors communication with CPLD using SMBUS
Tonar, Karel ; Rumánek, Jaroslav (referee) ; Kováč, Michal (advisor)
The goal of bachelor’s thesis is the introduction with two - wire circuit communication on the SMBUS, it is concretely related to alternate communication of FPGA with thermal sensors. The bachelor’s thesis also contains the choice of optimal thermal sensor, the proposal of module for measuring the temperature and proposal of programme for Programmable Logical Device. The programme processes data from the modules of temperature measurement and data are indicate on LED display. The programme makes it possible to display minimum, maximum and average temperature during certain time interval. All of programmes are implemented for logical device in VDHL language. The thermometer sends data to Personal Computer over UART interface. There is temperature displayed and storaged once again. During working on this bachelor’s thesis was used SPARTAN-3 starter board and design system Xilinx ISE 9.2i.
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Transformation from C to VHDL Language
Mecera, Martin ; Kolář, Dušan (referee) ; Masařík, Karel (advisor)
The thesis describes the process of transformation of the behavior of processor described in C language into VHDL language. Individual steps of automatized transformation are compared to manual design of processor. The thesis highlights advantages of the internal representation of program in the form of graph. Optimizations based on various factors are introduced in this thesis. One of them are algebraic modifications of expressions. The time of computation or space requirements of the circuit can be lowered by proper aplication of properties of math operators - associativity, comutativity and distributivity. Special attention is payed to optimizations, that make use of parallelism of operations for the process of planning. Algorithms of time-constrained scheduling and resource-constrained scheduling are discussed. The end of this thesis is devoted to resource allocation.
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Transformation between the Microprocessor's Description Language and the Hardware Language
Novotný, Tomáš ; Masařík, Karel (referee) ; Hruška, Tomáš (advisor)
The Master's thesis Transformation of the microprocessor's description language to the hardware description language is aimed at design of application specific microprocessors with using ISAC language. It deals with design and implementation of transformation which converts description of microprocessor in ISAC language into equivalent description in VHDL language. The chapter Summary of research problems describes chosen problems, showing up some notions connected with problems and presents suggestion of transformation mentioned above. The chapter Suggestion of solution presents new extension of ISAC language. There is also described the way of design solution of transformation and solution of implementation of VHDL generator which performs transformation. Conclusion of thesis discusses next points of future work reached results.
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Digital Programmable Building Blocks with the Residue Number Representation
Sharoun, Assaid Othman ; Mikula, Vladimír (referee) ; Šimčák, Marek (referee) ; Musil, Vladislav (advisor)
V systému s kódy zbytkových tříd je základem skupina navzájem nezávislých bází. Číslo ve formátu integer je reprezentováno kratšími čísly integer, které získáme jako zbytky všech bází, a aritmetické operace probíhají samostatně na každé bázi. Při aritmetických operacích nedochází k přenosu do vyšších řádů při sčítání, odečítání a násobení, které obvykle potřebují více strojového času. Srovnávání, dělení a operace se zlomky jsou komplikované a chybí efektivní algoritmy. Kódy zbytkových tříd se proto nepoužívají k numerickým výpočtům, ale jsou velmi užitečné pro digitální zpracování signálu. Disertační práce se týká návrhu, simulace a mikropočítačové implementace funkčních bloků pro digitální zpracování signálu. Funkční bloky, které byly studovány jsou nově navržené konvertory z binarní do reziduální reprezentace a naopak, reziduální sčítačka a násobička. Nově byly také navržené obslužné algoritmy.
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Sample assignments in VHDL
Huzlík, Petr ; Macho, Tomáš (referee) ; Holek, Radovan (advisor)
This bachelor’s study connects on semestral project and is focused on VHDL language and FPGA and CPLD circuits by Xilinx. The aim of this study is to describe how to work with profossional design tool WebPack. Documents detaily describes how to create new project on advanced level - with emphasis on methodiology and examples from practice in VHDL lenguage.
|
|
|
Thermal sensors communication with CPLD using SMBUS
Tonar, Karel ; Rumánek, Jaroslav (referee) ; Kováč, Michal (advisor)
The goal of bachelor’s thesis is the introduction with two - wire circuit communication on the SMBUS, it is concretely related to alternate communication of FPGA with thermal sensors. The bachelor’s thesis also contains the choice of optimal thermal sensor, the proposal of module for measuring the temperature and proposal of programme for Programmable Logical Device. The programme processes data from the modules of temperature measurement and data are indicate on LED display. The programme makes it possible to display minimum, maximum and average temperature during certain time interval. All of programmes are implemented for logical device in VDHL language. The thermometer sends data to Personal Computer over UART interface. There is temperature displayed and storaged once again. During working on this bachelor’s thesis was used SPARTAN-3 starter board and design system Xilinx ISE 9.2i.
|
|
|
Additional LCD Display for Laboratory Kit with a Programmable Device
Pajskr, Jaroslav ; Kubíček, Michal (referee) ; Kolouch, Jaromír (advisor)
The main part of the digital application is its user interface. Users can check the status of the programme or change its state. There are many ways to obtain a suitable interface. During the design stage the simplest interface is chosen that provides the necessary functions. In most cases the interface contains a display. This diploma thesis deals with the design of an extension board to plug in a display to a programmable device, a control algorithm for the display and the design of a simple display interface. There are two ways to design software. The first of them is achieved by the processor PicoBlaze, which contains all the required functions. The second solution is by the state machine written in VHDL language. Both solutions can be used in the same way, but the latter solution is quicker and requires less hardware resources.
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